欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1S25F672I7N 参数 Datasheet PDF下载

EP1S25F672I7N图片预览
型号: EP1S25F672I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 25660-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用: LTE可编程逻辑
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1S25F672I7N的Datasheet PDF文件第77页浏览型号EP1S25F672I7N的Datasheet PDF文件第78页浏览型号EP1S25F672I7N的Datasheet PDF文件第79页浏览型号EP1S25F672I7N的Datasheet PDF文件第80页浏览型号EP1S25F672I7N的Datasheet PDF文件第82页浏览型号EP1S25F672I7N的Datasheet PDF文件第83页浏览型号EP1S25F672I7N的Datasheet PDF文件第84页浏览型号EP1S25F672I7N的Datasheet PDF文件第85页  
Stratix Architecture  
The DSP block consists of the following elements:  
Multiplier block  
Adder/output block  
Multiplier Block  
The DSP block multiplier block consists of the input registers, a  
multiplier, and pipeline register for pipelining multiply-accumulate and  
multiply-add/subtract functions as shown in Figure 2–32.  
Figure 2–32. Multiplier Sub-Block within Stratix DSP Block  
sign_a (1)  
sign_b (1)  
aclr[3..0]  
clock[3..0]  
ena[3..0]  
shiftin A  
shiftin B  
D
Q
Data A  
Result  
to Adder  
blocks  
ENA  
D
Q
ENA  
CLRN  
Optional  
CLRN  
Multiply-Accumulate  
and Multiply-Add  
Pipeline  
D
Q
Data B  
ENA  
CLRN  
shiftout B shiftout A  
Note to Figure 2–32:  
(1) These signals can be unregistered or registered once to match data path pipelines if required.  
Altera Corporation  
July 2005  
2–57  
Stratix Device Handbook, Volume 1