欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1S25F672I7N 参数 Datasheet PDF下载

EP1S25F672I7N图片预览
型号: EP1S25F672I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 25660-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用: LTE可编程逻辑
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1S25F672I7N的Datasheet PDF文件第84页浏览型号EP1S25F672I7N的Datasheet PDF文件第85页浏览型号EP1S25F672I7N的Datasheet PDF文件第86页浏览型号EP1S25F672I7N的Datasheet PDF文件第87页浏览型号EP1S25F672I7N的Datasheet PDF文件第89页浏览型号EP1S25F672I7N的Datasheet PDF文件第90页浏览型号EP1S25F672I7N的Datasheet PDF文件第91页浏览型号EP1S25F672I7N的Datasheet PDF文件第92页  
Digital Signal Processing Block  
Output Selection Multiplexer  
The outputs from the various elements of the adder/output block are  
routed through an output selection multiplexer. Based on the DSP block  
operational mode and user settings, the multiplexer selects whether the  
output from the multiplier, the adder/subtractor/accumulator, or  
summation block feeds to the output.  
Output Registers  
Optional output registers for the DSP block outputs are controlled by four  
sets of control signals: clock[3..0], aclr[3..0], and ena[3..0].  
Output registers can be used in any mode.  
Modes of Operation  
The adder, subtractor, and accumulate functions of a DSP block have four  
modes of operation:  
Simple multiplier  
Multiply-accumulator  
Two-multipliers adder  
Four-multipliers adder  
1
Each DSP block can only support one mode. Mixed modes in the  
same DSP block is not supported.  
Simple Multiplier Mode  
In simple multiplier mode, the DSP block drives the multiplier sub-block  
result directly to the output with or without an output register. Up to four  
18 × 18-bit multipliers or eight 9 × 9-bit multipliers can drive their results  
directly out of one DSP block. See Figure 2–35.  
2–64  
Stratix Device Handbook, Volume 1  
Altera Corporation  
July 2005