Stratix Device Handbook, Volume 1
Mode 2–36
Port I/O Standards 2–102
Row
&
Column
Interface
Unit
I/O Standards Supported for Enhanced PLL
Pins 2–94
Signals 2–43
Parity Bit Support 2–24
Shift Register
Lock Detect
&
Programmable Gated
Locked 2–98
Memory Configuration 2–26
Support 2–25
Simple Dual-Port & Single-Port Memory
Configurations 2–23
PLL Locations 2–84
Programmable Bandwidth 2–91
Programmable Delay Chain 2–111
Programmable Duty Cycle 2–98
Reconfiguration 2–90
Stratix
IOE
in
DDR
Input
I/O
Configuration 2–112
Stratix IOE in DDR Output I/O
Configuration 2–114
T
TriMatrix Memory 2–21
Testing
Temperature Sensing Diode 3–13
True
Dual-Port
Memory
Configuration 2–22
Electrical Characteristics 3–14
External 3–14
Temperature vs. Temperature-Sensing Diode
Voltage 3–15
O
Ordering Information 5–1
Device Pin-Outs 5–1
Packaging Ordering Information 5–2
Reference & Ordering Information 5–1
Output Registers 2–64
Timing
DSP
Block Internal Timing
Microparameter
Descriptions 4–23
Output Selection Multiplexer 2–64
Microparameters 4–29
Dual-Port RAM Timing Microparameter
Waveform 4–27
External Timing in Stratix Devices 4–33
High-Speed I/O Timing 4–87
P
Packaging
High-Speed
Timing
Specifications
&
BGA Package Sizes 1–4
Device Speed Grades 1–5
FineLine BGA Package Sizes 1–5
PCI-X 1.0 Specifications 4–10
Phase Shifting 2–103
Terminology 4–87
Internal Parameters 4–22
IOE Internal Timing Microparameter
Descriptions 4–22
LE Internal Timing Microparameters 4–28
Logic Elements Internal Timing Microparam-
eter Descriptions 4–22
Model 4–19
PLL Timing 4–94
PLL
Advanced Clear & Enable Control 2–98
Dynamically Programmable Counters & De-
lays in Stratix Device Enhanced
PLLs 2–91
Preliminary & Final 4–19
Enhanced
Stratix Device Timing Model Status 4–19
Stratix JTAG
Fast PLLs 2–81
Fast PLL 2–100
Timing Parameters & Values 3–4
TriMatrix Memory
Channel Layout EP1S10, EP1S20 or
EP1S25 Devices 2–138
Channel Layout EP1S30 to EP1S80
Devices 2–139
TriMatrix Memory Features 2–21
Index–6
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
