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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Device Handbook, Volume 1  
Fast Regional Clock External I/O Timing  
Parameters 4–49  
Global Clock External I/O Timing  
Parameters 4–50  
I
I/O  
Standards  
1.5-V 4–14, 4–15  
Regional Clock External I/O Timing  
Parameters 4–50  
EP1S60 Devices  
Column Pin  
Fast Regional Clock External I/O Timing  
I/O Specifications 4–4  
I/O Specifications 4–4  
I/O Specifications 4–3  
1.8-V  
2.5-V  
Parameters 4–51  
Global Clock External I/O Timing  
Parameters 4–52  
Regional Clock External I/O Timing  
Parameters 4–51  
3.3-V 4–13  
LVDS I/O Specifications 4–6  
PCI Specifications 4–9  
PCML Specifications 4–8  
Advanced I/O Standard Support 2–122  
Column I/O Block Connection to the  
Interconnect 2–107  
M-RAM  
Interface Locations 2–38  
Row Pin  
Column Pin  
Fast Regional Clock External I/O Timing  
Parameters 4–52  
Global Clock External I/O Timing  
Parameters 4–53  
Regional Clock External I/O Timing  
Parameters 4–53  
Input Delay Adders 4–66  
Control Signal Selection per IOE 2–109  
CTT I/O Specifications 4–16  
Differential  
LVDS  
Input  
On-Chip  
Termination 2–128  
External I/O Delay Parameters 4–66  
GTL+ I/O Specifications 4–10  
High-Speed  
Support 2–130  
HyperTransport  
Specifications 4–9  
I/O Banks 2–125  
I/O Structure 2–104  
I/O Support by Bank 2–126  
IOE Structure 2–105  
LVCMOS Specifications 4–3  
LVDS Performance on Fast PLL  
Input 2–103  
EP1S80 Devices  
Column Pin  
Fast Regional Clock External I/O Timing  
Differential  
I/O  
Parameters 4–54  
Global Clock External I/O Timing  
Parameters 4–55  
Regional Clock External I/O Timing  
Parameters 4–54  
Technology  
Global Clock External I/O Timing  
Parameters 4–56  
Row Pin  
Fast Regional Clock External I/O Timing  
Parameters 4–55  
Regional Clock External I/O Timing  
Parameters 4–56  
LVPECL Specifications 4–8  
LVTTL Specifications 4–3  
MultiVolt I/O Interface 2–129  
MultiVolt I/O Support 2–130  
Output Delay Adders for Fast Slew Rate  
on Column Pins 4–68  
Output Delay Adders for Fast Slew Rate  
on Row Pins 4–69  
H
HSTL  
Class I Specifications 4–14, 4–15  
Class II Specifications 4–14, 4–15  
Output Delay Adders for Slow Slew Rate  
on Column Pins 4–70  
Package Options & I/O Pin Counts 1–4  
Receiver Input Waveforms for Differential  
Index–4  
Altera Corporation  
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