Index
Open-Drain Output 2–120
A
Power Sequencing & Hot Socketing 2–140
Programmable Drive Strength 2–119
Programmable Pull-Up Resistor 2–122
Simple Multiplier Mode 2–64
Single-Port Mode 2–51
Accumulator 2–63
Adder/Output Blocks 2–61
Adder/Subtractor
2–63
Accumulator
Slew-Rate Control 2–120
Two-Multipliers
2–63
AGP 1x Specifications 4–13
AGP 2x Specifications 4–13
Architecture 2–1
Adder Mode 2–67
Adder Mode Implementing Complex
Multiply 2–68
36 x 36 Multiply Mode 2–66
addnsub Signal 2–8
Block Diagram 2–2
C
Bus Hold 2–121
Class I Specifications 4–11, 4–12
Class II Specifications 4–11, 4–12, 4–13
Clocks
Byte Alignment 2–140
Carry-Select Chain 2–11
Clear & Preset Logic Control 2–13
Combined Resources 2–78
Dedicated Circuitry 2–137
Device Resources 2–3
Device Routing Scheme 2–20
Digital Signal Processing Block 2–52
Direct Link Connection 2–5
Dynamic Arithmetic Mode 2–10
in LE 2–11
Clock Feedback 2–96
Clock Multiplication & Division 2–88, 2–101
Clock Switchover
2–88
Delay 2–97
EP1S10, EP1S20 & EP1S25
Device I/O Clock Groups
2–80
EP1S25, EP1S20 & EP1S10 Device Fast Clock
Pin Connections to Fast Regional
Clocks 2–77
EP1S30 Device Fast Regional Clock Pin Con-
nections to Fast Regional Clocks 2–78
EP1S30, EP1S40, EP1S60, EP1S80
Device I/O Clock Groups
2–81
Four-Multipliers
Adder Mode 2–68
Functional Description 2–1
LAB
Interconnects 2–4
Logic Array Blocks 2–3
Structure 2–4
LE Operating Modes 2–8
Logic Elements 2–6
Modes of Operation 2–64
Multiplier Size & Configurations per DSP
block 2–70
Multiply-Accumulator Mode 2–67
MultiTrack Interconnect 2–14
Normal Mode 2–9
External Clock
Inputs 2–102
Outputs 2–92, 2–103
Outputs for Enhanced PLLs 11 & 12 2–95
Outputs for PLLs 5 & 6 2–93
Fast Regional Clock External I/O Timing
Parameters 4–34
Fast Regional Clock Network 2–76
in LE 2–9
Altera Corporation
Index–1
ALTERA [ ALTERA CORPORATION ]
