Functional Description
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR SDRAM,
FCRAM, ZBT, and QDR SRAM devices.
High-speed serial interface channels support transfers at up to 840 Mbps
using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O
standards.
Figure 2–1 shows an overview of the Stratix device.
Figure 2–1. Stratix Block Diagram
M4K RAM Blocks
for True Dual-Port
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
IOEs Support DDR, PCI, GTL+, SSTL-3,
Memory & Other Embedded SSTL-2, HSTL, LVDS, LVPECL, PCML,
Memory Functions
HyperTransport & other I/O Standards
IOEs
LABs
IOEs
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IOEs
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IOEs
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M-RAM Block
IOEs
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IOEs
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IOEs
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IOEs
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DSP
Block
2–2
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
