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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 4–11. 3.3-V PCML Specifications  
Symbol  
Parameter  
Conditions  
Minimum Typical Maximum  
Unit  
V
VCCIO  
I/O supply voltage  
3.135  
300  
3.3  
3.465  
600  
V
ID (peak-  
to-peak)  
Input differential voltage  
swing (single-ended)  
mV  
VICM  
Input common mode  
voltage  
1.5  
3.465  
500  
50  
V
VOD  
Output differential voltage  
(single-ended)  
300  
370  
mV  
mV  
V
Δ VOD  
VOCM  
Δ VOCM  
Change in VOD between  
high and low  
Output common mode  
voltage  
2.5  
2.85  
3.3  
Change in VOCM between  
high and low  
50  
mV  
VT  
R1  
Output termination voltage  
VCCIO  
50  
V
Output external pull-up  
resistors  
45  
45  
55  
55  
Ω
R2  
Output external pull-up  
resistors  
50  
Ω
Table 4–12. LVPECL Specifications  
Symbol  
Parameter  
Conditions  
Minimum Typical Maximum  
Unit  
V
VCCIO  
I/O supply voltage  
3.135  
300  
3.3  
3.465  
1,000  
V
ID (peak-  
to-peak)  
Input differential voltage  
swing (single-ended)  
mV  
VICM  
Input common mode  
voltage  
1
2
V
mV  
V
VOD  
VOCM  
RL  
Output differential voltage RL = 100 Ω  
(single-ended)  
525  
1.5  
90  
700  
1.7  
970  
1.9  
110  
Output common mode  
voltage  
RL = 100 Ω  
Receiver differential input  
resistor  
100  
Ω
4–8  
Altera Corporation  
January 2006  
Stratix Device Handbook, Volume 1  
 
 
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