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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC & Switching Characteristics  
Table 4–10. 3.3-V LVDS I/O Specifications (Part 2 of 2)  
Symbol  
Parameter  
Conditions  
Minimum Typical Maximum  
Unit  
VICM  
Input common mode  
voltage (6)  
LVDS  
0.3 V VID 1.0 V  
W = 1 through 10  
100  
1,600  
1,100  
1,100  
250  
1,100  
1,800  
1,600  
1,600  
mV  
LVDS  
0.3 V VID 1.0 V  
W = 1 through 10  
mV  
mV  
mV  
LVDS  
0.2 V VID 1.0 V  
W = 1  
LVDS  
0.1 V VID 1.0 V  
W = 2 through 10  
VOD (1)  
Δ VOD  
VOCM  
Δ VOCM  
RL  
Output differential voltage RL = 100 Ω  
(single-ended)  
375  
1,200  
100  
550  
50  
mV  
mV  
mV  
mV  
Ω
Change in VOD between  
high and low  
RL = 100 Ω  
RL = 100 Ω  
Output common mode  
voltage  
1,125  
90  
1,375  
50  
Change in VOCM between RL = 100 Ω  
high and low  
Receiver differential input  
discrete resistor (external  
to Stratix devices)  
110  
Altera Corporation  
January 2006  
4–7  
Stratix Device Handbook, Volume 1  
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