I/O Structure
Programmable Pull-Up Resistor
Each Stratix device I/O pin provides an optional programmable pull-up
resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO
level of the output pin’s bank. Table 2–30 shows which pin types support
the weak pull-up resistor feature.
Table 2–30. Programmable Weak Pull-Up Resistor Support
Pin Type
Programmable Weak Pull-Up Resistor
I/O pins
v
CLK[15..0]
FCLK
v
FPLL[7..10]CLK
Configuration pins
JTAG pins
v (1)
Note to Table 2–30:
(1) TDO pins do not support programmable weak pull-up resistors.
Advanced I/O Standard Support
Stratix device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
LVTTL
LVCMOS
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X 1.0
3.3-V AGP (1× and 2×)
LVDS
LVPECL
3.3-V PCML
HyperTransport
Differential HSTL (on input/output clocks only)
Differential SSTL (on output column clock pins only)
GTL/GTL+
1.5-V HSTL Class I and II
2–122
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
