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EP1K30TC144-3N 参数 Datasheet PDF下载

EP1K30TC144-3N图片预览
型号: EP1K30TC144-3N
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件LTE
文件页数/大小: 86 页 / 1204 K
品牌: ALTERA [ ALTERA CORPORATION ]
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ACEX 1K Programmable Logic Device Family Data Sheet  
If necessary, all EABs in a device can be cascaded to form a single RAM  
block. EABs can be cascaded to form RAM blocks of up to 2,048 words  
without impacting timing. Altera software automatically combines EABs  
to meet a designers RAM specifications.  
EABs provide flexible options for driving and controlling clock signals.  
Different clocks and clock enables can be used for reading and writing to  
the EAB. Registers can be independently inserted on the data input, EAB  
output, write address, write enable signals, read address, and read enable  
signals. The global signals and the EAB local interconnect can drive  
write-enable, read-enable, and clock-enable signals. The global signals,  
dedicated clock pins, and EAB local interconnect can drive the EAB clock  
signals. Because the LEs drive the EAB local interconnect, the LEs can  
control write-enable, read-enable, clear, clock, and clock-enable signals.  
An EAB is fed by a row interconnect and can drive out to row and column  
interconnects. Each EAB output can drive up to two row channels and up  
to two column channels; the unused row channel can be driven by other  
LEs. This feature increases the routing resources available for EAB  
outputs (see Figures 2 and 4). The column interconnect, which is adjacent  
to the EAB, has twice as many channels as other columns in the device.  
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Logic Array Block  
An LAB consists of eight LEs, their associated carry and cascade chains,  
LAB control signals, and the LAB local interconnect. The LAB provides  
the coarse-grained structure to the ACEX 1K architecture, facilitating  
efficient routing with optimum device utilization and high performance.  
Figure 7 shows the ACEX 1K LAB.  
Altera Corporation  
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