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EP1K30TC144-3N 参数 Datasheet PDF下载

EP1K30TC144-3N图片预览
型号: EP1K30TC144-3N
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件LTE
文件页数/大小: 86 页 / 1204 K
品牌: ALTERA [ ALTERA CORPORATION ]
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ACEX 1K Programmable Logic Device Family Data Sheet  
EABs can be used to implement synchronous RAM, which is easier to use  
than asynchronous RAM. A circuit using asynchronous RAM must  
generate the RAM write enable signal, while ensuring that its data and  
address signals meet setup and hold time specifications relative to the  
write enable signal. In contrast, the EABs synchronous RAM generates its  
own write enable signal and is self-timed with respect to the input or write  
clock. A circuit using the EAB’s self-timed RAM must only meet the setup  
and hold time specifications of the global clock.  
When used as RAM, each EAB can be configured in any of the following  
sizes: 256 × 16; 512 × 8; 1,024 × 4; or 2,048 × 2. Figure 5 shows the ACEX 1K  
EAB memory configurations.  
Figure 5. ACEX 1K EAB Memory Configurations  
2,048 × 2  
256 × 16  
512 × 8  
1,024 × 4  
Larger blocks of RAM are created by combining multiple EABs. For  
example, two 256 × 16 RAM blocks can be combined to form a 256 × 32  
block, and two 512 × 8 RAM blocks can be combined to form a  
512 × 16 block. Figure 6 shows examples of multiple EAB combination.  
Figure 6. Examples of Combining ACEX 1K EABs  
256 × 32  
512 × 16  
256 × 16  
256 × 16  
512 × 8  
512 × 8  
12  
Altera Corporation