ACEX 1K Programmable Logic Device Family Data Sheet
Figure 3. ACEX 1K EAB in Dual-Port RAM Mode
Port A
address_a[]
Port B
address_b[]
data_b[]
data_a[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
Figure 4. ACEX 1K Device in Single-Port RAM Mode
Dedicated Inputs
& Global Signals
Dedicated
Clocks
Chip-Wide
Reset
Row Interconnect
13
2
4
4, 8, 16, 32
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
D
Q
8, 4, 2, 1
Data Out
D
Q
4, 8
EAB Local
Interconnect (1)
Address
D
Q
8, 9, 10, 11
4, 8, 16, 32
Write Enable
D
Q
Column Interconnect
Note:
(1) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
Altera Corporation
11
ALTERA [ ALTERA CORPORATION ]
