Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
1–21
Pin Description
An initiate configuration (nINIT_CONF) JTAG instruction can be added to your
programming file in the Quartus II software by enabling the Initiate configuration
after programming option in the Programmer options window (Options menu).
Programming via External Flash Interface
This method allows parallel programming of the flash memory (using the 16-bit data
bus). An external processor or FPGA acts as the flash controller and has access to
programming data (via a communication link such as UART, Ethernet, and PCI). In
addition to the program, erase, and verify operations, the external flash interface
supports block/sector protection instructions.
f
For information about protection commands, areas, and lock bits, refer to the
appropriate flash data sheets.
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■
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For Micron flash-based EPC4, refer to the Micron Flash Memory MT28F400B3 Data
Sheet at www.micron.com.
For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory
Used in EPC16 Devices at www.sharpsma.com.
For the Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3,
28F320B3, 28F640B3 Datasheet, visit www.intel.com.
External flash interface programming is only allowed when the configuration
controller has relinquished flash access (by tri-stating its internal interface). If the
controller has not relinquished flash access (during configuration or JTAG-based ISP),
you must hold the controller in reset before initiating external programming. The
controller can be reset by holding the FPGA nCONFIGline at a logic low level. This
keeps the controller in reset by holding the nSTATUS-OEline low, allowing external
flash access.
1
If initial programming of the enhanced configuration device is done in-system via the
external flash interface, the controller must be kept in reset by driving the FPGA
nCONFIGline low to prevent contention on the flash interface.
Pin Description
Table 1–8 through Table 1–10 describe the enhanced configuration device pins. These
tables include configuration interface pins, external flash interface pins, JTAG
interface pins, and other pins.
Table 1–8. Configuration Interface Pins (Part 1 of 2)
Pin Name
Pin Type
Description
DATA[7..0]
Output
Configuration data output bus. DATAchanges on each falling edge of DCLK.
DATAis latched into the FPGA on the rising edge of DCLK.
DCLK
Output
The DCLKoutput pin from the enhanced configuration device serves as the FPGA
configuration clock. DATAis latched by the FPGA on the rising edge of DCLK.
© December 2009 Altera Corporation
Configuration Handbook (Complete Two-Volume Set)
ALTERA [ ALTERA CORPORATION ]
