Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
1–19
Functional Description
Table 1–6. Stratix Compression Ratios (Note 1)
Item
Logic Utilization
Minimum
Average
64%
98%
1.9
Compression Ratio
% Size Reduction
Note to Table 1–6:
2.3
47%
57%
(1) These numbers are preliminary. They are intended to serve as a guideline, not a specification.
Programmable Configuration Clock
The configuration clock (DCLK) speed is user programmable. One of two clock sources
can be used to synthesize the configuration clock; a programmable oscillator or an
external clock input pin (EXCLK). The configuration clock frequency can be further
synthesized using the clock divider circuitry. This clock can be divided by the N
counter to generate your DCLKoutput. The N divider supports all integer dividers
between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock
divisions other than non-integer divisions is 50% (for the non-integer dividers, the
duty cycle will not be 50%). Refer to Figure 1–5 for a block diagram of the clock
divider unit.
Figure 1–5. Clock Divider Unit
Configuration Device
Clock Divider Unit
External Clock
(Up to 100 MHz)
Divide
by N
DCLK
10 MHz
33 MHz
50 MHz
66 MHz
Internal Oscillator
The DCLKfrequency is limited by the maximum DCLKfrequency the FPGA supports.
f
The maximum DCLKinput frequency supported by the FGPA is specified in the
appropriate FPGA family chapter in the Configuration Handbook.
© December 2009 Altera Corporation
Configuration Handbook (Complete Two-Volume Set)
ALTERA [ ALTERA CORPORATION ]
