1–6
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
Table 1–3.
Enhanced Configuration Devices Flash Memory (Part 2 of 2)
Flash Memory
Device
EPC16
Grade
Commercial
Industrial
Commercial/
Industrial
Note to
(1) For more information, refer to the Process Change Notification
Package
UBGA 88
UBGA 88
PQFP 100
Leaded
Intel
or Sharp
Intel
or Sharp
Intel
or Sharp
Lead-Fee
Intel
or Sharp
Intel
Intel
www.altera.com/support.
Enhanced configuration devices have a 3.3-V core and I/O interface. The controller
chip is a synchronous system that implements the various interfaces and features.
shows a block diagram of the enhanced configuration device. The
controller chip features three separate interfaces:
■
■
■
A configuration interface between the controller and the Altera FPGAs
A JTAG interface on the controller that enables ISP of the flash memory
An external flash interface that the controller shares with an external processor, or
FPGA implementing a Nios
®
embedded processor (interface available after ISP
and configuration)
Figure 1–1.
Enhanced Configuration Device Block Diagram
JTAG/ISP Interface
Enhanced Configuration Device
Shared Flash
Interface
Flash
Controller
FPGA
Shared Flash Interface
ALTERA [ ALTERA CORPORATION ]
