1–2
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
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Supports ISP via Jam Standard Test and Programming Language (STAPL)
Supports JTAG boundary scan
nINIT_CONF
pin allows private JTAG instruction to start FPGA configuration
Internal pull-up resistor on
nINIT_CONF
always enabled
User programmable weak internal pull-up resistors on
nCS
and
OE
pins
Internal weak pull-up resistors on external flash interface address and control
lines, bus hold on data lines
Standby mode with reduced power consumption
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f
For more information about FPGA configuration schemes and advanced features,
refer to the appropriate FPGA family chapter in the
Functional Description
The Altera enhanced configuration device is a single-device, high-speed, advanced
configuration solution for very high-density FPGAs. The core of an enhanced
configuration device is divided into two major blocks: a configuration controller and a
flash memory. The flash memory is used to store configuration data for systems made
up of one or more Altera FPGAs. Unused portions of the flash memory can be used to
store processor code or data that can be accessed via the external flash interface after
FPGA configuration is complete.
summarizes the features of Altera
configuration devices and the amount of configuration space they hold.
Table 1–1.
Altera Configuration Devices
Memory Size
(bits)
4,194,304
8,388,608
16,777,216
On-Chip
Decompression
Support
Yes
Yes
Yes
ISP
Support
Yes
Yes
Yes
Cascading
Support
No
No
No
Operating
Voltage (V)
3.3
3.3
3.3
Device
EPC4
EPC8
EPC16
Reprogrammable
Yes
Yes
Yes
lists the supported configuration devices required to configure an ACEX 1K,
APEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Arria GX, Cyclone,
Cyclo
ne
II
,
FLEX 10K, FLEX 10KA, FLEX 10KE, Stratix, Stratix GX, Stratix II, Stratix II
GX, or Mercury device.
ALTERA [ ALTERA CORPORATION ]
