Preliminary Information
Cyclone FPGA Family Data Sheet
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the IOH/IOL
of the standard. Using minimum settings provides signal slew rate control
to reduce system noise and signal overshoot. Table 14 shows the possible
settings for the I/O standards with drive strength control.
Table 14. Programmable Drive Strength
I/O Standard
IOH/IOL Current Strength Setting (mA)
LVTTL (3.3 V)
4
8
12
16
24
2
LVCMOS (3.3 V)
LVTTL (2.5 V)
4
8
12
2
8
12
16
2
LVTTL (1.8 V)
8
12
2
LVCMOS (1.5 V)
4
8
Open-Drain Output
Cyclone devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
