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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Preliminary Information  
Cyclone FPGA Family Data Sheet  
A path in which a pin directly drives a register may require a  
programmable delay to ensure zero hold time, whereas a path in which a  
pin drives a register through combinatorial logic may not require the  
delay. Programmable delays decrease input-pin-to-logic-array and IOE  
input register delays. The Quartus II Compiler can program these delays  
to automatically minimize setup time while providing a zero hold time.  
Programmable delays can increase the register-to-pin delays for output  
registers. Table 12 shows the programmable delays for Cyclone devices.  
Table 12. Cyclone Programmable Delay Chain  
Programmable Delays  
Quartus II Logic Option  
Input pin to logic array delay  
Input pin to input register delay  
Output pin delay  
Decrease input delay to internal cells  
Decrease input delay to input registers  
Increase delay to output pin  
There are two paths in the IOE for a combinatorial input to reach the logic  
array. Each of the two paths can have a different delay. This allows the  
designer to adjust delays from the pin to internal LE registers that reside  
in two different areas of the device. The designer sets the two  
combinatorial input delays by selecting different delays for two different  
paths under the Decrease input delay to internal cells logic option in the  
Quartus II software. When the input signal requires two different delays  
for the combinatorial input, the input register in the IOE is no longer  
available.  
The IOE registers in Cyclone devices share the same source for clear or  
preset. The designer can program preset or clear for each individual IOE.  
The designer can also program the registers to power up high or low after  
configuration is complete. If programmed to power up low, an  
asynchronous clear can control the registers. If programmed to power up  
high, an asynchronous preset can control the registers. This feature  
prevents the inadvertent activation of another device’s active-low input  
upon power up. If one register in an IOE uses a preset or clear signal then  
all registers in the IOE must use that same signal if they require preset or  
clear. Additionally a synchronous reset signal is available to the designer  
for the IOE registers.  
External RAM Interfacing  
Cyclone devices support DDR SDRAM and FCRAM interfaces at up to  
133 MHz through dedicated circuitry.  
Altera Corporation  
51  
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