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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Preliminary Information  
Cyclone FPGA Family Data Sheet  
Figure 20. Read/Write Clock Mode in Simple Dual-Port Mode  
Note (1)  
6 LAB Row  
Clocks  
Memory Block  
256 × 16  
512 × 8  
6
1,024 × 4  
2,048 × 2  
4,096 × 1  
data[ ]  
D
ENA  
Q
Data In  
To MultiTrack  
Interconnect  
Data Out  
D
Q
ENA  
address[ ]  
Read Address  
D
Q
Q
Q
ENA  
wraddress[ ]  
Write Address  
Byte Enable  
Read Enable  
D
ENA  
byteena[ ]  
rden  
D
ENA  
D
Q
ENA  
wren  
rdclken  
Write  
Pulse  
Generator  
D
ENA  
Q
wrclken  
wrclock  
Write Enable  
rdclock  
Note to Figure 20:  
(1) All registers shown except the rden register have asynchronous clear ports.  
Single-Port Mode  
The M4K memory blocks also support single-port mode, used when  
simultaneous reads and writes are not required. See Figure 21. A single  
M4K memory block can support up to two single-port mode RAM blocks  
if each RAM block is less than or equal to 2K bits in size.  
Altera Corporation  
33  
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