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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Preliminary Information  
Cyclone FPGA Family Data Sheet  
Clear & Preset Logic Control  
LAB-wide signals control the logic for the register’s clear and preset  
signals. The LE directly supports an asynchronous clear and preset  
function. The register preset is achieved through the asynchronous load of  
a logic high. The direct asynchronous preset does not require a NOT-gate  
push-back technique. Cyclone devices support simultaneous preset/  
asynchronous load and clear signals. An asynchronous clear signal takes  
precedence if both signals are asserted simultaneously. Each LAB  
supports up to two clears and one preset signal.  
In addition to the clear and preset ports, Cyclone devices provide a chip-  
wide reset pin (DEV_CLRn) that resets all registers in the device. An option  
set before compilation in the Quartus II software controls this pin. This  
chip-wide reset overrides all other control signals.  
In the Cyclone architecture, connections between LEs, M4K memory  
blocks, and device I/O pins are provided by the MultiTrack interconnect  
structure with DirectDriveTM technology. The MultiTrack interconnect  
consists of continuous, performance-optimized routing lines of different  
speeds used for inter- and intra-design block connectivity. The Quartus II  
Compiler automatically places critical design paths on faster  
interconnects to improve design performance.  
MultiTrack  
Interconnect  
DirectDrive technology is a deterministic routing technology that ensures  
identical routing resource usage for any function regardless of placement  
within the device. The MultiTrack interconnect and DirectDrive  
technology simplify the integration stage of block-based designing by  
eliminating the re-optimization cycles that typically follow design  
changes and additions.  
The MultiTrack interconnect consists of row and column interconnects  
that span fixed distances. A routing structure with fixed length resources  
for all devices allows predictable and repeatable performance when  
migrating through different device densities. Dedicated row  
interconnects route signals to and from LABs, PLLs, and M4K memory  
blocks within the same row. These row resources include:  
Direct link interconnects between LABs and adjacent blocks  
R4 interconnects traversing four blocks to the right or left  
The direct link interconnect allows an LAB or M4K memory block to drive  
into the local interconnect of its left and right neighbors. Only one side of  
a PLL block interfaces with direct link and row interconnects. The direct  
link interconnect provides fast communication between adjacent LABs  
and/or blocks without using row interconnect resources.  
Altera Corporation  
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