Cyclone FPGA Family Data Sheet
Preliminary Information
All embedded blocks communicate with the logic array similar to LAB-to-
LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row
and column interconnects and has local interconnect regions driven by
row and column interconnects. These blocks also have direct link
interconnects for fast connections to and from a neighboring LAB.
Table 5 shows the Cyclone device’s routing scheme.
Table 5. Cyclone Device Routing Scheme
Source
Destination
LUT Chain
v
v
v
Register Chain
Local Interconnect
v
v
v
v
Direct Link
v
Interconnect
R4 Interconnect
C4 Interconnect
LE
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
M4K RAM Block
PLL
Column IOE
Row IOE
v
v
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Altera Corporation
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