Cyclone Device Handbook, Volume 1
External Clock Inputs
Each PLL supports single-ended or differential inputs for source-
synchronous receivers or for general-purpose use. The dedicated clock
pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also
act as LVDS input pins. See Figure 2–25.
Table 2–8 shows the I/O standards supported by PLL input and output
pins.
Table 2–8. PLL I/O Standards
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
CLK Input
v
EXTCLK Output
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
LVDS
v
SSTL-2 class I
v
SSTL-2 class II
SSTL-3 class I
v
v
SSTL-3 class II
Differential SSTL-2
v
For more information on LVDS I/O support, see “LVDS I/O Pins” on
page 2–54.
External Clock Outputs
Each PLL supports one differential or one single-ended output for source-
synchronous transmitters or for general-purpose external clocks. If the
PLL does not use these PLL_OUTpins, the pins are available for use as
general-purpose I/O pins. The PLL_OUTpins support all I/O standards
shown in Table 2–8.
The external clock outputs do not have their own VCC and ground voltage
supplies. Therefore, to minimize jitter, do not place switching I/O pins
next to these output pins. The EP1C3 device in the 100-pin TQFP package
2–36
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
