Global Clock Network & Phase-Locked Loops
Table 2–7. Global Clock Network Sources (Part 2 of 2)
Source
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7
Dual-Purpose DPCLK0 (3)
v
Clock Pins
DPCLK1 (3)
v
DPCLK2
DPCLK3
DPCLK4
DPCLK5 (3)
DPCLK6
DPCLK7
v
v
v
v
v
v
Notes to Table 2–7:
(1) EP1C3 devices only have one PLL (PLL 1).
(2) EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1and CLK3.
(3) EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5pins.
Clock Multiplication & Division
Cyclone PLLs provide clock synthesis for PLL output ports using
m/(n × post scale counter) scaling factors. The input clock is divided by
a pre-scale divider, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match fIN × (m/n). Each output port has
a unique post-scale counter to divide down the high-frequency VCO. For
multiple PLL outputs with different frequencies, the VCO is set to the
least-common multiple of the output frequencies that meets its frequency
specifications. Then, the post-scale dividers scale down the output
frequency for each output port. For example, if the output frequencies
required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the
least-common multiple in the VCO's range).
Each PLL has one pre-scale divider, n, that can range in value from 1 to
32. Each PLL also has one multiply divider, m, that can range in value
from 2 to 32. Global clock outputs have two post scale G dividers for
global clock outputs, and external clock outputs have an E divider for
external clock output, both ranging from 1 to 32. The Quartus II software
automatically chooses the appropriate scaling factors according to the
input frequency, multiplication, and division values entered.
Altera Corporation
January 2007
2–35
Preliminary
ALTERA [ ALTERA CORPORATION ]
