Cyclone Device Handbook, Volume 1
Figure 2–26 shows the PLL global clock connections.
Figure 2–26. Cyclone PLL Global Clock Connections
G1
G3
G5
G7
G0
G2
G4
G6
g0
g1
e
g0
g1
e
CLK0
CLK2
PLL1
PLL2
CLK1 (1)
CLK3 (2)
PLL1_OUT (3), (4)
PLL2_OUT (3), (4)
Notes to Figure 2–26:
(1) PLL 1 supports one single-ended or LVDS input via pins CLK0and CLK1.
(2) PLL2 supports one single-ended or LVDS input via pins CLK2and CLK3.
(3) PLL1_OUTand PLL2_OUTsupport single-ended or LVDS output. If external output is not required, these pins are
available as regular user I/O pins.
(4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the
144-pin TQFP package does not support external clock output from PLL2.
Table 2–7 shows the global clock network sources available in Cyclone
devices.
Table 2–7. Global Clock Network Sources (Part 1 of 2)
Source
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7
PLL Counter
Output
PLL1 G0
PLL1 G1
PLL2 G0 (1)
PLL2 G1 (1)
CLK0
v
v
v
v
v
v
v
v
v
v
v
v
v
Dedicated
Clock Input
Pins
v
CLK1 (2)
CLK2
v
v
CLK3 (2)
2–34
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
