Cyclone FPGA Family Data Sheet
Preliminary Information
Tables 55 through 56 show the external timing parameters on column and
row pins for EP1C12 devices.
Table 55. EP1C12 Column Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.187
0.000
2.000
2.363
0.000
2.000
2.535
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.965
5.592
5.592
4.401
6.192
6.192
4.845
6.798
6.798
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.152
0.000
0.500
3.570
3.570
1.260
0.000
0.500
3.933
3.933
1.368
0.000
0.500
4.297
4.297
1.943
2.142
2.344
Table 56. EP1C12 Row Pin Global Clock External I/O Timing Parameters
Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.308
0.000
2.000
2.502
0.000
2.000
2.694
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.827
5.413
5.413
4.243
5.988
5.988
4.666
6.570
6.570
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.273
0.000
0.500
3.391
3.391
1.399
0.000
0.500
3.729
3.729
1.527
0.000
0.500
4.069
4.069
1.805
1.984
2.165
84
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
