Preliminary Information
Cyclone FPGA Family Data Sheet
Tables 57 through 58 show the external timing parameters on column and
row pins for EP1C20 devices.
Table 57. EP1C20 Column Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.226
0.000
2.000
2.406
0.000
2.000
2.585
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.926
5.553
5.553
4.358
6.149
6.149
4.795
6.748
6.748
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.138
0.000
0.500
3.584
3.584
1.244
0.000
0.500
3.949
3.949
1.349
0.000
0.500
4.316
4.316
1.957
2.158
2.363
Table 58. EP1C20 Row Pin Global Clock External I/O Timing Parameters
Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.361
0.000
2.000
2.561
0.000
2.000
2.763
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.774
5.360
5.360
4.184
5.929
5.929
4.597
6.501
6.501
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.273
0.000
0.500
3.391
3.391
1.399
0.000
0.500
3.729
3.729
1.527
0.000
0.500
4.069
4.069
1.805
1.984
2.165
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by speed
grade independent of device density.
Altera Corporation
85
ALTERA [ ALTERA CORPORATION ]
