Cyclone FPGA Family Data Sheet
Preliminary Information
Table 48 shows the external I/O timing parameters when using global
clock networks.
Table 48. Cyclone Global Clock External I/O Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions
tINSU
Setup time for input or bidirectional pin using IOE input
register with global clock fed by CLKpin
tINH
Hold time for input or bidirectional pin using IOE input
register with global clock fed by CLKpin
tOUTCO
tXZ
Clock-to-output delay output or bidirectional pin using IOE CLOAD = 10 pF
output register with global clock fed by CLKpin
Synchronous column IOE output enable register to output
CLOAD = 10 pF
CLOAD = 10 pF
pin disable delay using global clock fed by CLKpin
tZX
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by CLKpin
tINSUPLL
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
tINHPLL
tOUTCOPLL
tXZPLL
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
Clock-to-output delay output or bidirectional pin using IOE CLOAD = 10 pF
output register with global clock enhanced PLL with default
phase setting
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by enhanced PLL
with default phase setting
CLOAD = 10 pF
tZXPLL
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by enhanced PLL
with default phase setting
CLOAD = 10 pF
Notes to Table 48:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II
software to verify the external timing for any pin.
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Altera Corporation
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