Cyclone FPGA Family Data Sheet
Preliminary Information
Table 43. Routing Delay Internal Timing Microparameter Descriptions
Symbol Parameter
tR4
tC4
tLOCAL
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Local interconnect delay
Figure 37 shows the memory waveforms for the M4K timing parameters
shown in Table 42.
Figure 37. Dual-Port RAM Timing Microparameter Waveform
wrclock
tWEREH
tWERESU
wren
tWADDRH
tWADDRSU
an-1
an
a0
a1
a2
a3
a4
a5
wraddress
data-in
a6
tDATAH
din-1
din4
din5
din6
din
tDATASU
rdclock
tWEREH
tWERESU
rden
tRC
rdaddress
bn
b1
b2
b3
b0
tDATACO1
doutn-1
doutn
dout0
reg_data-out
doutn-2
tDATACO2
doutn
doutn-1
dout0
unreg_data-out
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