Cyclone FPGA Family Data Sheet
Preliminary Information
Table 35. SSTL-3 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
Termination voltage
3.0
VREF – 0.05
1.3
3.3
VREF
1.5
3.6
V
V
V
V
V
V
V
VTT
VREF
VIH
VREF + 0.05
1.7
Reference voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.2
–0.3
VCCIO + 0.3
VREF – 0.2
VIL
VOH
VOL
IOH = –8 mA (9)
IOL = 8 mA (9)
VTT + 0.6
VTT – 0.6
Table 36. SSTL-3 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
Termination voltage
3.0
VREF – 0.05
1.3
3.3
VREF
1.5
3.6
V
V
V
V
V
V
V
VTT
VREF
VIH
VREF + 0.05
1.7
Reference voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.2
–0.3
VCCIO + 0.3
VREF – 0.2
VIL
VOH
VOL
IOH = –16 mA (9) VTT + 0.8
IOL = 16 mA (9)
VTT – 0.8
Table 37. Bus Hold Parameters
Parameter Conditions
VCCIO Level
1.8 V
Unit
1.5 V
Min Max
2.5 V
3.3 V
Min
Max
Min
Max
Min
Max
Low sustaining VIN > VIL
current (maximum)
High sustaining VIN < VIH
current (minimum)
Low overdrive 0 V < VIN
current VCCIO
High overdrive 0 V < VIN
current VCCIO
30
50
70
µA
µA
µA
µA
–30
–50
–70
<
<
200
300
500
–200
–300
–500
72
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