Cyclone FPGA Family Data Sheet
Preliminary Information
Table 29. 1.8-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
1.65
0.65 × VCCIO
–0.3
1.95
2.25
V
V
V
V
V
VIH
VIL
0.35 × VCCIO
VOH
VOL
IOH = –2 to –8 mA (9) VCCIO – 0.45
IOL = 2 to 8 mA (9)
0.45
Table 30. 1.5-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
1.4
1.6
V
V
V
V
V
VIH
VIL
0.65 × VCCIO VCCIO + 0.3
–0.3
0.35 × VCCIO
VOH
VOL
IOH = –2 mA (9)
IOL = 2 mA (9)
0.75 × VCCIO
0.25 × VCCIO
Table 31. 2.5-V LVDS I/O Specifications
Note (10)
Symbol
Parameter
Conditions
Minimum Typical Maximum
Unit
VCCIO
I/O supply voltage
2.375
250
2.5
2.625
550
50
V
VOD
Differential output voltage RL = 100 Ω
mV
mV
∆ VOD
Change in VOD between
high and low
RL = 100 Ω
VOS
Output offset voltage
RL = 100 Ω
RL = 100 Ω
1.125
1.25
1.375
50
V
∆ VOS
Change in VOS between
high and low
mV
VTH
VIN
Differential input threshold VCM = 1.2 V
–100
0.0
100
2.4
mV
V
Receiver input voltage
range
RL
Receiver differential input
resistor
90
100
110
Ω
70
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
