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EP1C12F256C8N 参数 Datasheet PDF下载

EP1C12F256C8N图片预览
型号: EP1C12F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 第一节的Cyclone FPGA系列数据手册 [Section I. Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 106 页 / 1386 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1
Table 1–1. Cyclone Device Features (Part 2 of 2)
Feature
Total RAM bits
PLLs
Maximum user I/O pins
(1)
Note to
Table 1–1:
(1)
This parameter includes global clock pins.
EP1C3
59,904
1
104
EP1C4
78,336
2
301
EP1C6
92,160
2
185
EP1C12
239,616
2
249
EP1C20
294,912
2
301
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine
®
BGA packages (see
Tables 1–2
through
1–3).
Table 1–2. Cyclone Package Options and I/O Pin Counts
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Notes to
Table 1–2:
(1)
(2)
TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).
100-Pin TQFP 144-Pin TQFP 240-Pin PQFP
256-Pin
324-Pin
400-Pin
(1)
(1), (2)
(1)
FineLine BGA FineLine BGA FineLine BGA
65
104
98
185
173
185
185
249
249
233
301
301
Vertical migration means you can migrate a design from one device to
are subsets or supersets for a given package across device densities. The
largest density in any package has the highest number of power pins; you
must use the layout for the largest planned density in a package to
provide the necessary power pins for migration.
For I/O pin migration across densities, cross-reference the available I/O
pins using the device pin-outs for all planned densities of a given package
type to identify which I/O pins can be migrated. The Quartus
®
II
software can automatically cross-reference and place all pins for you
when given a device migration list. If one device has power or ground
pins, but these same pins are user I/O on a different device that is in the
migration path,the Quartus II software ensures the pins are not used as
user I/O in the Quartus II software. Ensure that these pins are connected
1–2
Preliminary
Altera Corporation
May 2008