Document Revision History
to the appropriate plane on the board. The Quartus II software reserves
I/O pins as power pins as necessary for layout with the larger densities
in the same package having more power pins.
Table 1–3. Cyclone QFP and FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length
×
width
(mm
×
mm)
100-Pin
TQFP
0.5
256
16×16
144-Pin
TQFP
0.5
484
22×22
240-Pin
PQFP
0.5
1,024
34.6×34.6
256-Pin
FineLine
BGA
1.0
289
17×17
324-Pin
FineLine
BGA
1.0
361
19×19
400-Pin
FineLine
BGA
1.0
441
21×21
Document
Revision History
Table 1–4
shows the revision history for this document.
Table 1–4. Document Revision History
Date and
Document
Version
May 2008
v1.5
January 2007
v1.4
August 2005
v1.3
October 2003
v1.2
September
2003 v1.1
May 2003 v1.0
Changes Made
Minor textual and style changes.
Added document revision history.
Minor updates.
Added 64-bit PCI support information.
●
●
Summary of Changes
—
—
—
—
—
—
Updated LVDS data rates to 640 Mbps from 311 Mbps.
Updated RSDS feature information.
Added document to Cyclone Device Handbook.
Altera Corporation
May 2008
1–3
Preliminary
ALTERA [ ALTERA CORPORATION ]
