3–2
Chapter 3: Configuration and Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Arria GX JTAG Instructions
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation and permits an
initial data pattern to be output at the device pins. Also used by
the SignalTap II embedded logic analyzer.
EXTEST (1)
00 0000 1111
11 1111 1111
Allows external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing
test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation.
USERCODE
00 0000 0111
Selects the 32-bit USERCODEregister and places it between the
TDIand TDOpins, allowing the USERCODEto be serially shifted
out of TDO.
IDCODE
00 0000 0110
00 0000 1011
Selects the IDCODEregister and places it between TDIand TDO,
allowing IDCODEto be serially shifted out of TDO.
HIGHZ (1)
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in
the boundary-scan register.
ICR instructions
—
Used when configuring an Arria GX device via the JTAG port with
a USB-BlasterTM, MasterBlasterTM, ByteBlasterMVTM
,
EthernetBlasterTM, or ByteBlaster II download cable, or when
using a .jam or .jbc via an embedded processor or JRunnerTM.
PULSE_NCONFIG
00 0000 0001
00 0000 1101
Emulates pulsing the nCONFIGpin low to trigger
reconfiguration even though the physical pin is unaffected.
CONFIG_IO (2)
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during
configuration. Once issued, the CONFIG_IOinstruction holds
nSTATUSlow to reset the configuration device. nSTATUSis
held low until the IOE configuration register is loaded and the
TAP controller state machine transitions to the UPDATE_DR
state.
Notes to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information about using the CONFIG_IOinstruction, refer to the MorphIO: An I/O Reconfiguration Solution for Altera Devices
White Paper.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
