2–104
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved as such that each I/O bank on
the left side of the device has one receiver channel and one transmitter channel per
LAB row. Figure 2–81 shows the fast PLL and channel layout in the EP1AGX20C,
EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices. Figure 2–82 shows the
fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.
Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices (Note 1)
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
2
Fast
PLL 1
Fast
PLL 2
Quadrant
Quadrant
LVDS
Clock
DPA
Clock
4
Note to Figure 2–81:
(1) For the number of channels each device supports, refer to Table 2–30.
Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices (Note 1)
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
2
Fast
PLL 1
Fast
PLL 2
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 8
Note to Figure 2–82:
(1) For the number of channels each device supports, refer to Table 2–30 through Table 2–34.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
