Chapter 3: Configuration and Testing
3–3
SignalTap II Embedded Logic Analyzer
The Arria GX device instruction register length is 10 bits and the USERCODEregister
length is 32 bits. Table 3–2 and Table 3–3 show the boundary-scan register length and
device IDCODEinformation for Arria GX devices.
Table 3–2. Arria GX Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
1320
1320
1668
1668
2016
Table 3–3. 2-Bit Arria GX Device IDCODE
IDCODE (32 Bits)
Device
Manufacturer Identity
Version (4 Bits)
Part Number (16 Bits)
LSB (1 Bit)
(11 Bits)
EP1AGX20
0000
0000
0000
0000
0000
0010 0001 0010 0001
0010 0001 0010 0001
0010 0001 0010 0010
0010 0001 0010 0010
0010 0001 0010 0011
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
1
1
1
1
1
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
SignalTap II Embedded Logic Analyzer
Arria GX devices feature the SignalTap II embedded logic analyzer, which monitors
design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry.
You can analyze internal logic at speed without bringing internal signals to the I/O
pins. This feature is particularly important for advanced packages, such as FineLine
BGA (FBGA) packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Arria GX architecture are configured with
CMOS SRAM elements. Altera® FPGAs are reconfigurable and every device is tested
with a high coverage production test program so you do not have to perform fault
testing and can instead focus on simulation and design verification.
Arria GX devices are configured at system power up with data stored in an Altera
configuration device or provided by an external controller (for example, a MAX® II
device or microprocessor). You can configure Arria GX devices using the fast passive
parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous
(PPA), and JTAG configuration schemes. Each Arria GX device has an optimized
interface that allows microprocessors to configure it serially or in parallel, and
synchronously or asynchronously. The interface also enables microprocessors to treat
Arria GX devices as memory and configure them by writing to a virtual memory
location, making reconfiguration easy.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
