Features
Table 1–1. Arria GX Device Features (Part 2 of 2)
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
Feature
C
C
D
C
D
C
D
E
E
Source-
31
31
31
31
31, 42
31
31
42
47
synchronous
receive
channels
Source-
29
29
29
29
29, 42
29
29
42
45
synchronous
transmit
channels
M512 RAM
blocks (32 ×
18 bits)
166
118
1
197
140
1
313
242
2
326
252
2
478
400
4
M4K RAM
blocks (128 ×
36 bits)
M-RAM
blocks (4096
× 144 bits)
Total RAM
bits
1,229,184
40
1,348,416
56
2,475,072
104
2,528,640
128
4,477,824
176
Embedded
multipliers
(18 × 18)
DSP blocks
PLLs
10
4
14
4
26
32
4
44
8
4
4, 8
8
Maximum
230, 341
230
341
229
350, 514
229
350
514
538
user I/O pins
Arria GX devices are available in space-saving FBGA packages (refer to
Table 1–2). All Arria GX devices support vertical migration within the
same package. With vertical migration support, designers can migrate to
devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. For I/O pin migration
Altera Corporation
May 2008
1–3
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
