Arria GX Device Family Overview
■
Main device features:
●
TriMatrix memory consisting of three RAM block sizes to
implement true dual-port memory and first-in first-out (FIFO)
buffers with performance up to 380 MHz
●
Up to 16 global clock networks with up to 32 regional clock
networks per device
●
High-speed DSP blocks provide dedicated implementation of
multipliers, multiply-accumulate functions, and finite impulse
response (FIR) filters
●
Up to four enhanced PLLs per device provide spread spectrum,
programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
●
Support for numerous single-ended and differential I/O
standards
●
High-speed source-synchronous differential I/O support on up
to 47 channels
●
Support for source-synchronous bus standards, including SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI,
and CSIX-L1
●
Support for high-speed external memory including double data
rate (DDR and DDR2) SDRAM, and single data rate (SDR)
SDRAM
●
Support for multiple intellectual property megafunctions from
Altera
®
MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
)
●
Support for remote configuration updates
lists Arria GX device features for FineLine BGA (FBGA) with
flip-chip packages.
Table 1–1. Arria GX Device Features (Part 1 of 2)
EP1AGX20C
Feature
C
Package
484-pin,
780-pin (Flip-
chip)
8,632
21,580
4
600 Mbps to
3.125 Gbps
4
EP1AGX35C/D
C
484-pin
(Flip-
chip)
EP1AGX50C/D
C
484-pin
(Flip-
chip)
EP1AGX60C/D/E
C
484-
pin
(Flip-
chip)
EP1AGX90E
E
E
1152-pin
(Flip-chip)
D
780-pin
(Flip-
chip)
D
780-pin,
1152-pin
(Flip-
chip)
D
780-
pin
(Flip-
chip)
24,040
60,100
1152-
pin
(Flip-
chip)
ALMs
Equivalent
LEs
Transceiver
channels
Transceiver
data rate
13,408
33,520
8
4
20,064
50,160
8
4
36,088
90,220
12
12
600 Mbps to
3.125 Gbps
8
600 Mbps to 3.125
Gbps
600 Mbps to 3.125
Gbps
600 Mbps to 3.125
Gbps
1–2
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
