Arria GX Device Family Overview
■
Main device features:
●
TriMatrix memory consisting of three RAM block sizes to
implement true dual-port memory and first-in first-out (FIFO)
buffers with performance up to 380 MHz
●
●
Up to 16 global clock networks with up to 32 regional clock
networks per device
High-speed DSP blocks provide dedicated implementation of
multipliers, multiply-accumulate functions, and finite impulse
response (FIR) filters
●
Up to four enhanced PLLs per device provide spread spectrum,
programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
●
●
●
Support for numerous single-ended and differential I/O
standards
High-speed source-synchronous differential I/O support on up
to 47 channels
Support for source-synchronous bus standards, including SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI,
and CSIX-L1
●
●
Support for high-speed external memory including double data
rate (DDR and DDR2) SDRAM, and single data rate (SDR)
SDRAM
Support for multiple intellectual property megafunctions from
Altera® MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM
Support for remote configuration updates
)
●
Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with
flip-chip packages.
Table 1–1. Arria GX Device Features (Part 1 of 2)
EP1AGX20C
C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
E
Feature
C
D
C
D
C
D
E
Package
484-pin,
780-pin (Flip-
chip)
484-pin
(Flip-
chip)
780-pin
(Flip-
chip)
484-pin 780-pin,
484-
pin
(Flip-
chip)
780- 1152-
pin pin
(Flip- (Flip-
chip) chip)
1152-pin
(Flip-chip)
(Flip-
chip)
1152-pin
(Flip-
chip)
ALMs
8,632
13,408
33,520
20,064
50,160
24,040
60,100
36,088
90,220
Equivalent
LEs
21,580
Transceiver
channels
4
4
8
4
8
4
8
12
12
Transceiver
data rate
600 Mbps to 600 Mbps to 3.125 600 Mbps to 3.125
3.125 Gbps Gbps Gbps
600 Mbps to 3.125
Gbps
600 Mbps to
3.125 Gbps
1–2
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
