DC and Switching Characteristics
Table 4–123 shows the JTAG timing parameters and values for Arria GX
devices.
Table 4–123. Arria GX JTAG Timing Parameters and Values
Symbol
Parameter
Min Max Unit
tJCP
TCK clock period
30
12
12
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCK clock high time
tJCL
TCK clock low time
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
5
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
9
9
9
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
4
5
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
12
12
12
This chapter references the following documents:
Referenced
Documents
■
■
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
Arria GX Device Family Data Sheet in volume 1 of the Arria GX Device
Handbook
■
■
PowerPlay Early Power Estimator and PowerPlay Power Analyzer
PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook
Altera Corporation
May 2008
4–137
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
