External Memory Interface Specifications
Table 4–117. Fast PLL Specifications (Part 2 of 2)
Name
Description
Min
10
Typ
Max
Unit
ns
tARESET
Minimum pulse width on aresetsignal.
tARESET_RECONFIG
500
ns
Minimum pulse width on the aresetsignal
when using PLL reconfiguration. Reset the
PLL after scandonegoes high.
Note to Table 4–117:
(1) This is limited by the I/O fMAX
.
Tables 4–118 through 4–122 contain Arria GX device specifications for the
dedicated circuitry used for interfacing with external memory devices.
External
Memory
Interface
Table 4–118. DLL Frequency Range Specifications
Specifications
Frequency Mode
Frequency Range (MHz)
0
1
2
100 to 175
150 to 230
200 to 310
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) ,
Note (1)
Number of DQS Delay Buffer Stages
Commercial (ps)
Industrial (ps)
(2)
1
2
3
4
80
110
130
180
210
110
130
160
Notes to Table 4–119:
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
(2) Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
4–134
Altera Corporation
Arria GX Device Handbook, Volume 1
May 2008
ALTERA [ ALTERA CORPORATION ]
