DC and Switching Characteristics
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock
(tDQS_PSERR
)
Number of DQS Delay Buffer Stages
–6 Speed Grade (ps)
1
2
3
4
35
70
105
140
Table 4–121. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER
)
Mode
DQS Clock Skew Adder (ps)
4 DQ per DQS
9 DQ per DQS
18 DQ per DQS
36 DQ per DQS
40
70
75
95
Table 4–122. DQS Phase Offset Delay Per Stage (ps) Notes (1), (2), (3)
Positive Offset
Negative Offset
Speed Grade
Min
Max
Min
Max
-6
10
16
8
12
Notes to Table 4–122:
(1) The delay settings are linear.
(2) The valid settings for phase offset are -32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
Altera Corporation
May 2008
4–135
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
