FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 20. 5.0-V Device Capacitance of EPF10K10, EPF10K20 & EPF10K30 Devices
Note (9)
Max
Symbol
Parameter
Input capacitance
Conditions
Min
Unit
C
C
V
V
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
8
pF
pF
IN
IN
Input capacitance on dedicated
clock pin
12
INCLK
IN
C
Output capacitance
V
= 0 V, f = 1.0 MHz
8
pF
OUT
OUT
Table 21. 5.0-V Device Capacitance of EPF10K40, EPF10K50, EPF10K70 & EPF10K100 Devices Note (9)
Symbol
Parameter
Input capacitance
Conditions
Min
Max
Unit
C
C
V
V
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
10
15
pF
pF
IN
IN
Input capacitance on dedicated
clock pin
INCLK
IN
C
Output capacitance
V
= 0 V, f = 1.0 MHz
10
pF
OUT
OUT
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time is 100 ms. VCC must rise monotonically.
(5) Typical values are for TA = 25° C and VCC = 5.0 V.
(6) These values are specified under Table 18 on page 44.
(7) The IOH parameter refers to high-level TTL or CMOS output current.
(8) The IOL parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as
well as output pins.
(9) Capacitance is sample-tested only.
Altera Corporation
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