FLEX 10K Embedded Programmable Logic Family Data Sheet
In addition to the six clear and preset modes, FLEX 10K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 10 shows examples
of how to enter a section of a design for the desired functionality.
Figure 10. LE Clear & Preset Modes
Asynchronous Clear
Asynchronous Preset
Asynchronous Clear & Preset
labctrl1
VCC
PRN
Chip-Wide Reset
labctrl1 or
PRN
D
Q
labctrl2
D
Q
PRN
D
Q
CLRN
CLRN
labctrl1 or
labctrl2
labctrl2
Chip-Wide Reset
CLRN
Chip-Wide Reset
VCC
Asynchronous Load without Clear or Preset
Asynchronous Load with Clear
NOT
NOT
labctrl1
(Asynchronous
Load)
labctrl1
(Asynchronous
Load)
PRN
PRN
data3
(Data)
D
Q
data3
(Data)
D
Q
NOT
CLRN
CLRN
labctrl2
(Clear)
NOT
Chip-Wide Reset
Chip-WideReset
Asynchronous Load with Preset
NOT
labctrl1
(Asynchronous
Load)
labctrl2
(Preset)
PRN
D
Q
data3
(Data)
CLRN
NOT
Chip-Wide Reset
22
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
