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DSF10K 参数 Datasheet PDF下载

DSF10K图片预览
型号: DSF10K
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式可编程逻辑系列 [EMBEDDED PROGRAMMABLE LOGIC FAMILY]
分类和应用: 可编程逻辑
文件页数/大小: 138 页 / 1955 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 10K Embedded Programmable Logic Family Data Sheet  
Table 114 summarizes the ClockLock and ClockBoost parameters.  
Table 114. ClockLock & ClockBoost Parameters  
Symbol  
Parameter  
Min Typ  
Max Unit  
tR  
Input rise time  
Input fall time  
Input duty cycle  
2
2
ns  
ns  
tF  
tINDUTY  
fCLK1  
tCLK1  
fCLK2  
tCLK2  
45  
30  
55  
%
Input clock frequency (ClockBoost clock multiplication factor equals 1)  
Input clock period (ClockBoost clock multiplication factor equals 1)  
Input clock frequency (ClockBoost clock multiplication factor equals 2)  
Input clock period (ClockBoost clock multiplication factor equals 2)  
80  
MHz  
ns  
12.5  
16  
33.3  
50  
MHz  
ns  
20  
62.5  
±1  
fCLKDEV1 Input deviation from user specification in MAX+PLUS II (ClockBoost clock  
multiplication factor equals 1) (1)  
MHz  
fCLKDEV2 Input deviation from user specification in MAX+PLUS II (ClockBoost clock  
multiplication factor equals 2) (1)  
±0.5  
MHz  
tINCLKSTB Input clock stability (measured between adjacent clocks)  
100  
10  
1
ps  
µs  
ns  
%
tLOCK  
Time required for ClockLock or ClockBoost to acquire lock (2)  
Jitter on ClockLock or ClockBoost-generated clock (3)  
tJITTER  
tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock  
40  
50  
60  
Notes:  
(1) To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the  
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this  
frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency  
during device operation. Simulation does not reflect this parameter.  
(2) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If  
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during  
configuration, because the tLOCK value is less than the time required for configuration.  
(3) The tJITTER specification is measured under long-term observation.  
The supply power (P) for FLEX 10K devices can be calculated with the  
following equation:  
Power  
Consumption  
P = P  
+ P = (I  
+ I  
) × V + P  
INT  
IO  
CCSTANDBY  
CCACTIVE CC IO  
Typical I  
values are shown as I  
in the FLEX 10K 5.0-V  
CC0  
CCSTANDBY  
device DC operating conditions tables on pages 44, 47, and 50 of this data  
sheet. The I value depends on the switching frequency and the  
CCACTIVE  
application logic. This value is calculated based on the amount of current  
that each LE typically consumes. The P value, which depends on the  
IO  
device output load characteristics and switching frequency, can be  
calculated using the guidelines given in Application Note 74 (Evaluating  
Power for Altera Devices).  
118  
Altera Corporation  
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