FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 113. EPF10K250A Device External Bidirectional Timing Parameters
Note (1)
Symbol
Speed Grade
-2
Unit
-1
-3
Min
Max
Min
Max
Min
Max
t
t
t
t
t
9.3
0.0
2.0
10.6
0.0
12.7
0.0
ns
ns
ns
ns
ns
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
8.0
10.8
10.8
2.0
8.9
12.2
12.2
2.0
10.4
14.2
14.2
ZXBIDIR
Notes to tables:
(1) All timing parameters are described in Tables 32 through 38 in this data sheet.
(2) Using an LE to register the signal may provide a lower setup time.
(3) This parameter is specified by characterization.
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 31 illustrates the incoming and generated clock
specifications.
ClockLock &
ClockBoost
Timing
Parameters
Figure 31. Specifications for the Incoming & Generated Clocks
The t parameter refers to the nominal input clock period; the t parameter refers to the
I
O
nominal output clock period.
tCLK1
tINDUTY
tI ± fCLKDEV
Input
Clock
tR
tI
tI ± tINCLKSTB
tF
tOUTDUTY
ClockLock-
Generated
Clock
tO
tO + tJITTER tO – tJITTER
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117
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