3–6
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–4 and Figure 3–5 show the address clock enable waveform during read and
write cycles, respectively.
Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
rden
a0
a1
a2
a3
a4
a5
a6
addressstall
latched address
(inside memory)
a5
a1
a4
an
a0
q (synch)
dout0
dout1
dout4
doutn-1
doutn
doutn
dout1
dout1
dout1
dout1
dout0
dout4
dout1
q (asynch)
dout5
Figure 3–5. Cyclone III Device Family Address Clock Enable During Write Cycle Waveform
inclock
a0
00
a1
01
a2
02
a3
03
a4
04
a5
05
a6
06
wraddress
data
wren
addressstall
latched address
(inside memory)
a1
a4
03
a5
an
XX
a0
00
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
01
02
XX
XX
04
XX
XX
05
Mixed-Width Support
M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to “Memory Modes” on
page 3–7.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
