3–4
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Byte Enable Support
The Cyclone III device family M9K memory blocks support byte enables that mask
the input data so that only specific bytes of data are written. The unwritten bytes
retain the previous written value. The wrensignals, along with the byte-enable
(byteena) signals, control the write operations of the RAM block. The default value of
the byteenasignals is high (enabled), in which case writing is controlled only by the
wrensignals. There is no clear port to the byteenaregisters. M9K blocks support byte
enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
Byte enables operate in one-hot manner, with the LSB of the byteenasignal
corresponding to the least significant byte of the data bus. For example, if
byteena = 01and you are using a RAM block in ×18 mode, data[8..0]is enabled
and data[17..9]is disabled. Similarly, if byteena = 11, both data[8..0]and
data[17..9]are enabled. Byte enables are active high.
Table 3–2 lists the byte selection.
(1)
Table 3–2. byteena for Cyclone III Device Family M9K Blocks
Affected Bytes
byteena[3..0]
datain × 16
[7..0]
[15..8]
—
datain × 18
[8..0]
[17..9]
—
datain × 32
datain × 36
[8..0]
[0] = 1
[1] = 1
[7..0]
[15..8]
[17..9]
[2] = 1
[23..16]
[31..24]
[26..18]
[35..27]
[3] = 1
—
—
Note to Table 3–2:
(1) Any combination of byte enables is possible.
Figure 3–2 shows how the wrenand byteenasignals control the RAM operations.
(1)
Figure 3–2. Cyclone III Device Family byteena Functional Waveform
inclock
wren
rden
an
XXXX
XX
a0
10
a1
ABCD
01
a2
a0
a1
a2
address
data
XXXX
XX
11
byteena
FFFF
ABFF
contents at a0
FFFF
FFCD
ABFF
contents at a1
FFFF
ABFF
ABCD
contents at a2
q (asynch)
doutn
FFCD
ABCD
FFCD
ABCD
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
