High-Speed Differential Interfaces in Cyclone II Devices
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Maintain equal distance between traces in LVDS pairs, as much as
possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
Longer traces have more inductance and capacitance. These traces
should be as short as possible to limit signal integrity issues.
Place termination resistors as close to receiver input pins as possible.
Use surface mount components.
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Avoid 90° or 45° corners.
Use high-performance connectors.
Design backplane and card traces so that trace impedance matches
the connector’s and/or the termination’s impedance.
Keep equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths result in misplaced crossing points and decrease system
margins as the channel-to-channel skew (TCCS) value increases.
Limit vias because they cause discontinuities.
Use the common bypass capacitor values such as 0.001, 0.01, and
0.1 µF to decouple the high-speed PLL power and ground planes.
Keep switching transistor-to-transistor logic (TTL) signals away
from differential signals to avoid possible noise coupling.
Do not route TTL clock signals to areas under or above the
differential signals.
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Analyze system-level signals.
For PCB layout guidelines, see AN 224: High-Speed Board Layout
Guidelines.
Cyclone II differential I/O capabilities enable you to keep pace with
increasing design complexity. Support for I/O standards including
LVDS, LVPECL, RSDS, mini-LVDS, differential SSTL and differential
HSTL allows Cyclone II devices to fit into a wide variety of applications.
Taking advantage of these I/O capabilities and Cyclone II pricing allows
you to lower your design costs while remaining on the cutting edge of
technology.
Conclusion
Altera Corporation
February 2007
11–17
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
