Design Guidelines
Figure 11–17. Cyclone II High-Speed I/O Timing Budget Note (1)
Internal Clock Period
0.5 × TCCS
RSKM
SW
RSKM
0.5 × TCCS
Note to Figure 11–17:
(1) The equation for the high-speed I/O timing budget is: Period = 0.5/TCCS + RSKM + SW + RSKM + 0.5/TCCS.
This section provides guidelines for designing with Cyclone II devices.
Design
Guidelines
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the VCCIO supply, there are
restrictions on placement of single-ended I/O pins in relation to
differential pads.
f
See the guidelines in the Selectable I/O Standards in Cyclone II Devices
chapter in Volume 1 of the Cyclone II Device Handbook for placing single-
ended pads with respect to differential pads in Cyclone II devices.
Board Design Considerations
This section explains how to get the optimal performance from the
Cyclone II I/O interface and ensure first-time success in implementing a
functional design with optimal signal quality. The critical issues of
controlled impedance of traces and connectors, differential routing, and
termination techniques must be considered to get the best performance
from the IC. The Cyclone II device generates signals that travel over the
media at frequencies as high as 805 Mbps. Use the following general
guidelines for improved signal quality:
■
Base board designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
11–16
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
