High-Speed I/O Timing in Cyclone II Devices
Figures 11–14 and 11–15 show differential HSTL class I and II interfaces,
respectively.
Figure 11–14. Differential HSTL Class I Interface
VTT
VTT
50 Ω
50 Ω
Output Buffer
Receiver
Z
= 50 Ω
= 50 Ω
0
Z
0
Figure 11–15. Differential HSTL Class II Interface
VTT
VTT
VTT
VTT
50 Ω
50 Ω
50 Ω
50 Ω
Output Buffer
Receiver
Z
= 50 Ω
= 50 Ω
0
Z
0
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Cyclone II devices. LVDS, LVPECL,
RSDS, and mini-LVDS I/O standards enable high-speed data
transmission. Timing for these high-speed signals is based on skew
between the data and the clock signals.
High-Speed I/O
Timing in
Cyclone II
Devices
High-speed differential data transmission requires timing parameters
provided by integrated circuit (IC) vendors and requires consideration of
board skew, cable skew, and clock jitter. This section provides details on
high-speed I/O standards timing parameters in Cyclone II devices.
11–14
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
