PLLs & Clock Networks
Figure 2–40 shows a top-level diagram of the Stratix II device and PLL
floorplan.
Figure 2–40. PLL Locations
CLK[15..12]
11
5
7
10
FPLL7CLK
FPLL10CLK
CLK[8..11]
FPLL9CLK
1
2
4
3
CLK[3..0]
PLLs
FPLL8CLK
8
9
12
6
CLK[7..4]
Figures 2–41 and 2–42 shows the global and regional clocking from the
fast PLL outputs and the side clock pins.
2–60
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007